System-on-a-chip (soc) Verification Methods

The advent of system-on-a-chip (SoC) technology is a result of ever increasing transistor density. Unfortunately, this means that verification will pose the greatest problem to design because difficulties in verification scale faster than transistor technology. This paper provides evidence of this effect by citing industry trends, as well as discusses the potential pitfalls in SoC verification. Various SoC verification methods are offered by a number of industry groups such as Cadence, Synopsis, Mentor Graphics, and Motorola. These solutions generally offer theories based on divide-and-conquer and abstraction techniques. Specifically, Cadence offers the Unified Verification Methodology, which uses abstraction to check systems as design progresses instead of after the entire design is complete. Synopsis strongly encourages intellectual property (IP) reuse to allow for quick verification and gives guidelines to follow in order to create effective macros. Mentor Graphics joins Synopsis in support of reusable IP. However, Mentor Graphics is unique because they also believe that divide-and-conquer methods and specialized hardware will be important to overcome SoC verification. Motorola provides a practical viewpoint by demonstrating successful SoC designs by their own abstraction and divide-and-conquer techniques. In addition, notable insights from the University of Tennessee, Knoxville, who model SoC verification difficulties, and TIMA Laboratory in Grenoble, France, who provide algorithms that make SoC verification faster, are presented.